Senior Manager/Director, RTL Design (ASIC / VLSI / SoC) - Remote, US
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At Capgemini Engineering you will get to work on industry leading VLSI technologies and craft innovative solutions to enable industries/clients in diverse segments like (but not limited to) AI/ML, Cloud, Datacenter, 5G, computers, communications, mobility, automotive etc. You will work and partner with the best and brightest in the field.Summary:As the RTL lead for Pathfinding, you will work with customers directly in the initial phase of the engagement focusing on Tech Readiness of the program to be executed. This would include scoping the RTL requirements from customer and the sizing, resource estimates depending on technical details, known execution risks and mitigations aligned with customer. You should be able to lead the functional area (RTL) and represent Capgemini Engineering to the customer and vice versa. Internally you will draw out the program execution plan and work with implementation leads to draft SOW, milestones. After the Pathfinding/TR phase, you will own the RTL execution for the chip to meet the spec/requirements as aligned with all the stakeholdersThe RTL lead creates block designs from system requirements and spec requirements from architecture. Performs RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals.You will own/develop Microarchitecture and Logic Design and collaborate with functional leads to deliver design from Architecture to tape-out. RTL lead will work with chip leads, architects in implementation of chip /IP features, drive design reviews, test plan /validation reviews. Timely resolution of issues to enable high quality delivery on timeResponsibilities:
- Implement HW architecture from specification documents.
- Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL
- Develop and execute low power design (UPF/CPF).
- Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc.
- Work closely with DV team in reviewing test plans, and fixing design issues optimally
- Work closely with PV team to ensure RTL meets PPA goals
- Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties)
- Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
- Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
- Take ownership of tasks and drive tasks to closure.Qualifications:
- 12-15+ years of experience in Logic (RTL) Design
- Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
- Experience with advanced peripheral bus IP s such as GPIO, UART, SPI, SW, JTAG, and I2C.
- Strong fundamentals in VLSI design
- Strong problem-solving and data analysis skills
- Strong skills using scripting languages such as Perl, TCL, Python.
- Excellent interpersonal skills and able to work with remote teams
- Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with adata driven approach.
- Knowledge of low-speed bus protocols (AMBA/OCP) and high-speed serial protocols (PCIe/USB/Ethernet) willbe used at various stages of the design.Education:Bachelor s Degree in Electrical or Computer Engineering or related field
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